PhD
16 Years
DESIGN AND IMPLEMENTATION OF ADDER ARCHITECTURES AND ANALYSIS OF PERFORMANCE METRICS
Design and implementation of novel 32-bit mac unit for dsp applications 2.8×8 SFQ based Multiplier design using Verilog in Cadence.3.Realization of 8-Bit Pipelined RISC Processor using Verilog HDL.
@copyright 2026 KLE's P.C Jabin Science College (BCA) All Rights Reserved.
